A typical polar transmitter, such as for example described in X. Gao, E. Klumperink, M. Bohsali and B. Nauta, “A Low Noise Sub-Sampling PLL in Which Divider Noise is Eliminated and PD/CP Noise is Not Multiplied by N2”, IEEE Journal of Solid-State Circuits, vol. 44, no. 12, pp. 3253-3263, 2003, and shown schematically in FIG. 1, consists of a phase/frequency modulating phase-locked loop 4 (PLL) and an amplitude modulating digital power amplifier 16 (DPA) as a digital amplitude modulator (DAM). These two blocks are connected serially as shown in FIG. 1.
WO-A-01/24356 discloses a PLL for phase modulation in radio transmitters. The PLL comprises a DAM and a limiter to remove amplitude information from signal that is fed back into the phase detector in the PLL.
Such polar transmitters have the disadvantage that they are limited by the noise in the system, PLL and DPA bandwidth, both, phase/frequency modulator and DPA linearity. Furthermore, the DPA amplitude modulation can induce parasitic phase/frequency modulation, i.e. AM-to-PM distortion. Also, phase/frequency modulation can result in unwanted amplitude modulation, i.e. PM-to-AM distortion.